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JTAG Boundary-Scan Training Classes

 
     
     
 

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Free Boundary-Scan Training Classes

Corelis offers free three-day training classes that include a boundary-scan tutorial and hands-on lab exercises using Corelis ScanExpress hardware and software. The training class covers all aspects of boundary-scan testing using Corelis ScanExpress tools. Design for testability (DFT), JTAG embedded functional test (JET), in-system programming (ISP) and test procedure generation are also covered.

The training includes a combination of lectures, demonstrations, and hands-on exercises using actual hardware to provide you with an overview of ScanExpress test and ISP features and to have you run your own developed test.


Corelis Training Class Schedule and Location

2010 Schedule:

   January 12-14
   February 16-18
   March 16-18
   April 13-15
   May 11-13
   June 15-17
   July 13-15
   August 17-19
   September 14-16
   October 19-21
   November 16-18

Location: Corelis Headquarters, 12607 Hiddencreek Way, Cerritos, CA  90703

Register Now

Registration contact:
Corelis Training
email: training@corelis.com
Tel.: +1 (562) 926-6727
 


All Corelis training classes held at Corelis are at NO CHARGE!



Who should attend?

This class is intended for design engineers, test engineers, and managers who plan to use boundary-scan test methodology and the Corelis ScanExpress family of products. Previous knowledge of boundary-scan technology is not required.


What will you be able to do upon completion of the class?

Upon completion of the training you will be able to correctly implement boundary-scan DFT and ISP facilities into your new designs. You will also be able to develop boundary-scan test procedures on your own as well as in-system programming files for CPLDs and Flash memories.

Topics covered in the class include:

  • Introduction to boundary-scan

  • Design for boundary-scan testability Guidelines

  • Design for boundary-scan In-System Programming Strategy

  • Test generation and testing methods for boundary-scan-based designs

    • Test program generation methodology

    • Test program execution plan

    • Test program interactive debugging concepts

  • At-speed embedded functional testing using an on-board JTAG-based CPU

  • In-system programming of CPLDs and Flash memories tutorial

  • Hands-on individual lab exercises using real Units Under Test (UUTs) that will teach you:

    • How to generate and execute interconnect tests

    • How to test memory interconnects

    • How to test logic clusters

    • How to use an embedded processorís JTAG port for embedded functional testing

    • How to program CPLDs and Flash memories in circuit

    • How to troubleshoot a test procedure

You will become familiar with the entire Corelis ScanExpress product family, including:

  • ScanExpress TPG

  • ScanExpress JET

  • ScanExpress DFT Analyzer

  • ScanExpress Merge

  • ScanExpress Runner

  • ScanExpress ADO

  • ScanExpress Viewer

  • ScanExpress Debugger

  • ScanExpress Programmer

  • ScanExpress Flash Generator

 


Schedule, Registration, Cancellation, and General Information

For additional schedule and registration information about training classes, please contact:

Corelis Training
training@corelis.com
+1 (562) 926-6727

  • Classes are subject to cancellation two weeks prior to start date.

  • Classes held at the Corelis Headquarters are no-charge.

  • On-site training classes are available.  Contact your Corelis sales engineer or sales@corelis.com for scheduling and pricing information.

       

JTAG Training

 

Corelis Education



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