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Debug a Dead Board

Learn how to “Debug a Dead Board” using Corelis ScanExpress JTAG/boundary-scan and ScanExpress JET products in conjunction with a Blackhawk JTAG emulator.


What is a Dead Board?

“Dead” generally refers to a board that does not respond, initialize or power-up to an expected state. Failure modes can typically be broken down into two categories: hardware and software.

Hardware/Software Faults

 


Prototype Bring-up & Debug Cycle

Finished Assembly > Visual Inspection > Smoke Test > Voltage Test > Boot-Up > Debug

  • Visually check correct component installation

  • Verify no shorts on power rails to ground

  • Apply current-limited power to the board, ensure nothing gets hot, verify voltage levels

  • Load basic boot code and functional code to verify CPU and peripheral operation

 


Existing Test Tools

  • There are many tools that can assist in the debug process

  • Having the most efficient tool for the job saves engineering time

  • Knowing which tool to use at the right time is key

Multi-Meter, Oscilloscope, Logic Analyzer, Bus Analyzer, Real-Time Trace, Debugger, In-Circuit Emulator

 


Corelis Structural & Emulation Test Tools

Voltage Test > Structural Test > Emulation Test > Boot-Up

  • There Corelis directly replaces many traditional debug tools by providing automated test generation and low level diagnostic information saving valuable engineering time and effort

  • Structural testing identifies physical faults such as broken circuit traces, solder bridges and cold solder joints

  • Emulation testing verifies DSP operation and exercises peripheral interfaces at intended design speeds

 


JTAG Architechture

Structural Test
 

Main Building Blocks of a JTAG Device

  • JTAG Interface Pins

  • Test Data Registers

  • Instruction Register

  • TAP Controller

Main Building Blocks of a JTAG Device

JTAG Scan-Chain

Structural Test

JTAG Scan-Chain
 

JTAG Test Vectors

Structural Test

JTAG Test Vectors

 

Benefits of JTAG

  • JTAG provides the capability to test interconnects on a PC-board without physical test probes or test fixtures

  • Does not require the board to be in a bootable state for fault diagnostics

  • JTAG allows In-System Programming of devices such as Flash, CPLDs, FPGAs and Serial EEPROMs

 

JTAG Advantages

  • Automated test development for DSP initialization, memory and flash

  • Device level diagnostics

  • Customized diagnostic messages

  • JET rigorously exercises allexternal memory locations before execution of any boot code

  • Test vectors can be reused in production

 

JTAG and JET Fault Coverage

  • JTAG Pin Connectivity; Noisy Signals

  • Opens, Shorts & Stuck-At Conditions

  • DSP Initialization

  • Component Discovery and Identification

  • Bad Memory Locations

  • Flash Communication Problems

  • Timing Problems
     


JTAG Emulation Test

Emulation Test

JET uses a DSP’s JTAG debug port to perform:

  • DSP initialization

  • At-speed functional testing of DSP peripherals (memory, I/O)

  • In-System-Programming (ISP) of flash devices

JTAG Emulation Test

JTAG Emulation Test

JET Benefits

  • Does not require the board to be in a bootable state for fault diagnostics

  • Embedded tests are downloaded and run from on-chip DSP memory at-speed

  • Provides testability on all DSP addressable components by exercising their functionality

  • In-system programming at theoretical speeds reduces time waiting for code to download

JET Advantages

  • Automated test development for DSP initialization, memory and flash

  • Device level diagnostics

  • Customized diagnostic messages

  • JET rigorously exercises allexternal memory locations before execution of any boot code

  • Test vectors can be reused in production
     


Combining JTAG and JET

Structural Test > Emulation Test > Combined JTAG and JET
 

Feature JTAG Test Emulation Test Combined Test
Structural coverage Very Good Good Excellent
Functional coverage Low High High
Programming (ISP) time Average Excellent Excellent
Test time Fast Fast Fast
Test points required Very few Very few Very few
Test development Automatic Semi Auto Auto/Semi
Diagnostics Excellent Average Excellent

 

JTAG & JET Fault Coverage

  • JTAG Pin Connectivity; Noisy Signals

  • Opens, Shorts & Stuck-At Conditions

  • DSP Initialization

  • Component Discovery and Identification

  • Bad Memory Locations

  • Flash Communication Problems

  • Timing Problems
     


Case Study - Complex TI Target

  • Board includes twenty-six TI DaVinci processors

  • Board includes other JTAG and non-JTAG components

  • JTAG components include a PowerPC CPU and two FPGAs

  • Corelis JTAG tools are able to perform full interconnect and basic memory pin testing

  • JET to the rescue…JET emulation testing identified crosstalk and signal integrity issues on SDRAM memories that JTAG scans did not detect

TI Target

 

     

 

 

About Texas Instruments Developer Network

 
  Corelis is a member of the TI Developer Network, a community of respected, well-established companies offering products and services based on TI analog and digital technology. The Network provides a broad range of end-equipment solutions, embedded software, engineering services and development tools that help customers accelerate innovation to make the world smarter, healthier, safer, greener and more fun.  
 

 

About Blackhawk

 
  Blackhawk DSP
Blackhawk™ was the first to introduce a USB JTAG Emulator for Texas Instruments DSP’s and is a member of the Texas Instruments Third Party Developers Network.
 
 

 

About Corelis

 
  Corelis, Inc., a subsidiary of Electronic Warfare Associates, Inc., offers bus analysis tools, embedded test tools and the industry’s broadest line of JTAG/boundary-scan software and hardware products that combine exceptional ease-of-use with advanced technical innovation and unmatched customer service.  
 

 


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