Corelis JTAG tools provided real benefits for Ixia
Tests Double-Data Rate SDRAM memories
through Xilinx VertexE FPGAs
Located in
Calabasas, California,
Ixia is a
leading developer of sophisticated optical and electrical
network traffic performance analysis solutions. Mr. Xinchen
Wang, Hardware Engineer at Ixia, is responsible for JTAG testing
and verification for one of Ixia’s new interface load modules.
According to
Xinchen Wang, to achieve increased net coverage through JTAG
testing for Ixia’s new traffic generation and analysis tool, it
is important to first verify that all the FPGA’s external Double
Data Rate (DDR) SDRAM connections are properly placed and
functioning correctly to aide in further design
troubleshooting.
Corelis
proposed a ScanPlus solution tailored to meet Ixia’s
requirements. Corelis provided a PCI 1149.1 JTAG controller
with a pre-verified DDR SDRAM testing software package with some
minor updates to generate memory-testing vectors through JTAG
compatible Xilinx FPGAs. The generated vectors successfully
tested the interconnects between the FPGAs and the connections
to the DDR SDRAM; and furthermore, verified the general
functionality of the memory device according to its own
published specifications.
Xinchen Wang
puts it this way, “The Corelis ScanPlus boundary-scan
interconnect tester is also a highly effective memory test suite
that allowed us to reduce prototype debug time and improve our
time-to-market. The Corelis technical support team was extremely
helpful and committed to helping IXIA meet its project
dead-line.”
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