Who can benefit from using ScanExpress JET?
JET Supported Processors
JET utilizes a processor’s JTAG debug port to download and control native processor code where at-speed functional testing of a Unit Under Test (UUT) is performed. In addition to providing test coverage for non-JTAG components, this technology also allows programming of flash memories at their fastest theoretical programming speed.
Corelis pioneered JTAG emulation and has provided customers with thousands of JTAG emulators for many CPU types. Corelis is also the world leader in boundary-scan test tools. Combining these two technologies into one product provides customers with an integrated development and execution test environment with a single point of contact and support.
The JET testing method depends on the UUT having a JTAG-enabled processor (CPU) on-board. The CPU dedicated JTAG Test Access Port (TAP) is generally routed to a single emulation connector on the board. Other JTAG interconnect scan chains may be connected to different JTAG connectors which are used for boundary-scan testing.
The CPU debug TAP brings control and visibility of the processor itself to the host. This is the same TAP employed by JTAG emulators for software development and debug. Included are access to the CPU register/control structures, attached memory, and the ability to utilize the CPU debug running/stepping facilities for testing.
The JET method harnesses the power of the target embedded CPU to assist in the code download, device programming, and testing operations at full processing speed. Several basic features are available:
The host software uses these features to download test/diagnostics routines into the CPU’s cache memory and into the target memory. These routines execute at speed and pass the test results to the host.
There is no need to modify the on-board application software, typically stored in Flash memory. The Flash memory itself can be similarly programmed using the CPU as an algorithm expediter. This avoids the slower wiggling approach of JTAG Flash programming.
Connecting to the UUT
A board may include a single JTAG TAP that is dedicated to a specific CPU. This TAP is used for software debug and/or boundary-scan test. A board may also include multiple JTAG TAPs, one of them being used for software debug and/or boundary-scan test and the other TAPs being used for boundary-scan test.
Corelis’ JTAG controllers support multiple TAP configurations with a single controller. There is no need to switch cables or use relays when moving from a debug to test environment or switching from boundary-scan test to JTAG Embedded Test.
Figure 1 depicts connecting Corelis’ NetUSB-1149.1/E™ JTAG controller to a board that includes a CPU with a dedicated JTAG port, and additional boundary-scan compatible devices chained into separate JTAG ports.
Using ScanExpress JET
The ScanExpress JET tool is available as a stand-alone application or as a plug-in to ScanExpress TPG. Functional tests that are generated using ScanExpress JET are also compatible with the ScanExpress Runner test executive. Figure 2 depicts the ScanExpress JET GUI.
The ScanExpress JET Integrated Development Environment (IDE) consists of the following major functions:
ScanExpress JET has the ability to record all feature selections and file references to enable recalling a given project. This serves as a mechanism to quickly retest previous target boards as well as providing a starting point for migrating similar test scenarios.
When operating as a plug-in to ScanExpress TPG™, ScanExpress JET inherits the boundary-scan environment parameters, including all settings and files of the host application.
This constitutes a set of sequential screens which guide a user in selecting options and declaring device specific parameters. It collects all the information required to perform automatic testing using the JET methodology. It also includes optional JTAG operations to assure minimal board connectivity at the outset.
The major pieces of information required by the tool include:
The information collected becomes part of the project when saved.
Completion of the Preparation phase results in the automatic creation of scripts, download routines, and embedded test steps required to perform specific board testing.
The Test Steps screen lists the test steps automatically created during the preparation phase and provides controls to run tests on the target and view results. The steps can be invoked individually, run in their entirety or with an enabled subset, and can even be looped.
Progress while the steps are underway is also indicated.
This screen shows a PASS/FAIL indication summarizing the overall outcome of all enabled test operations. Detailed diagnostics of failure causes is displayed.
The Reports function provides access to test coverage statistics enabling the user to determine the overall testability utilizing ScanExpress JET. Included are merged coverage statistics showing how well testing confirms board operability. Coverage information includes both JET steps as well as legacy boundary-scan tests.
ScanExpress JET test steps can be executed from the ScanExpress Runner environment. ScanExpress JET will automatically pass the generated test files to ScanExpress Runner. Clicking on the Runner icon in the shortcut pane on the left side of the ScanExpress JET main window launches ScanExpress Runner.
Using ScanExpress Runner to execute boundary-scan tests in conjunction with JET based tests provides a single test environment for a complete test using both test methods. Verifying structural integrity with JTAG interconnection test prior to running JET functional tests results in better overall diagnostics during failure conditions.
Figure 3 shows a test procedure within ScanExpress Runner that contains both boundary-scan and JET functional tests.
Corelis Software/Hardware Flowchart
ScanExpress JET 13 Point Benefit
For complete information on ScanExpress JET, please refer to the detailed datasheet for this product.